ICE theory

The PCI communicates between the VRE and the ICE.

An IXH610 PCIe interface card (dolphin card) with updating EEPROM is used in the VRE.

• VRF function moves to the ICE PSC FPGA from the VRE in CAM configuration.

• (For Signa Architect, Artist, Pioneer, Voyager, and Premier systems) PCIe cable should connect to IDB PCIe connector instead of IMB.

• (For Discovery, Optima, SIGNA Creator / Explorer, SIGNA MR355 / MR360 systems) PCIe cable should connect to PCIe connector J55.

• (For Discovery and Optima systems with XGD gradients) PCIe cable should connect to PCIe connector J51.

• Direct USB Connection instead of Ethernet + Term Server.

• USB-Serial conversion on IMB.

• USB repeater boards exist on both the ICE & Host sides

• New Host-CPLD interface via USB.

Copper CAN connection:

• (For Pioneer and Voyager systems) Copper CAN: GP4 > RF Amp > ASC > DM > CabMon

• (For Signa Architect, Artist, Discovery, and Optima systems) Copper CAN: ICE > RF Amp > ASC > DM > CFB

Fiber CAN connection:

• (For Signa Architect, Artist, Pioneer, and Voyager systems) Fiber CAN: SRI4

• (For Discovery and Optima systems) CFB > SRI4, CFB > PAC > CFB > RF Hub, CFB > High Order Shim (optional) > CAN terminator

• Copper twin BNC clock connection instead of optical connector for enhanced reliability.

• Note: Forward production Architect and Artist systems eliminate the clock splitter.

• CLKS1 splits 80MHz clock from the Exciter to the ICE and receive chain.

(For Signa Architect, Artist, Pioneer, Voyager, and Premier systems) The RF analog signal from the MR coils is converted into a digital signal in the DPP (digitized per pin) and the digital data is sent to the iVRF within the ICE chassis thorough DVMRlink. See Receive Chain Theory for more information.

(For Discovery and Optima systems) The RF analog signal from the MR coils is sent to the iVRF within the ICE Chassis thorough DVMRlink. See Receive Chain Theory for more information.

The IMB is one of two boards that may exist in the ICE High Level Assembly (HLA). The IMB contains all of the base SSC functions and can operate with or without a daughter board in a system that requires 32 (or fewer) receive channels and up to two parallel transmit channels. The ICE Daughter Board (IDB) allows expansion of this system up to 128 receive channels and eight parallel transmit channels. See ICE daughter board (IDB) for more information about the IDB.

IMB features:

• P2020 Dual Core PowerPC with real-time VxWorks OS.

• High-speed PCIe replaced cPCI backplane.

• USB-to-serial on board for host communication.

• Sequencer, DVMRlink comm., VRF in one PSC FPGA

PSC FPGA

• iPSE

  • Sequence processor: Accesses DDR2 SDRAM to construct SSP/RF/Grad waveform data.

  • WARP: Applies rotation matrix for oblique scan, eddy current compensation for B0, B0 drift compensation.

  • SEU (sync exec unit): Synchronize sequence data playout on sequence bus with trigger and 4us tick.

• iHSS

  • Interfaces with four external and five internal DVMRlinks.

  • (For DPP receive chain systems) Delay module exists to establish synchronized DVMRlink communication from the IMB and IDB.

  • (For RRx receive chain systems) Delay module exists to establish synchronized DVMRlink communication from the IMB.

  • FDM as new function for data validity check which replaces monitor fifo in iPSE.

• iVRF

  • Decimation filter for received data from the receive chain.

  • R2 digital gain adjustment.

  • Two 16 channel-supported modules.

  • Filtered data DMA transfer to recon via PCIe.

Three identical REP FPGAs reside in the ICE daughter board, which supports the signal receive capability up to 96 channels and can generate up to six unique channels of RF data. When combined with the mother board, the ICE HLA can support 128 receive channels and generate eight unique RF data channels. Each FPGA has the DVMRlink communication with the PSC FPGA, which resides in the ICE mother board, and three external DVMRlink communications with remote devices.

The internal logic of the REP FPGA can be divided into two main functional blocks: iERF and iVRF.

• iERF

  • Expand DVMRlink communication with one DPP (up to 32 channels).

  • FDM (same function as in PSC FPGA).

• iVRF (completely identical to iVRF in PSC FPGA)

  • Decimation filter for received data from receive chain.

  • R2 digital gain adjustment.

  • Two 16 channel-supported modules.

  • Filtered data DMA transfer to recon via PCIe