• Topic ID: id_16157747
  • Version: 1.0
  • Date: Jul 7, 2018 4:29:22 PM

TGP Board Theory

1 FPGAs

The two FPGAs on the TGP board perform major functions of the board. These FPGAs are named LSCOM_CTRL and TRIG, respectively.

1.1 LSCOM_CTRL FPGA

This FPGA controls the LSCOM function. The TGP processor communicates with the ORP board via this LSCOM_CTRL FPGA and slip rings. It also transmits the EXP_ENBL hardware signal.

1.2 TRIG FPGA

This FPGA has the following functions:

  • Chip selection

  • Store of Revision No.

  • A/D conversion / Buffer circuits

  • Bounce elimination

  • Trigger sequence function

  • Output register

  • Status register

  • Interrupt control

  • Pulse generator for motor driver (not used)

  • Encoder pulse frequency divider (Axial, Cradle)

Some of the functions above are described in the sections below.

1.2.1 Store of Revision No.

The FPGA stores the part No., variation No., and revision No. of the TGP board.

1.2.2 A/D Conversion / Buffer Circuits

An A/D converter on the board converts the following analog signals being output from the FPGA device of the MSUB board:

  • Table position voltage (not used)

  • Cradle position voltage (not used)

  • Tilt position voltage (not used)

  • MSUB miscellaneous analog voltages

  • Power (24V) voltage

  • Power (12V) voltage

  • Power (5V) voltage

1.2.3 Trigger Sequence Function

The exposure command signal is activated when the enable bit has been activated and the selected synchronization signal is activated. The synchronization signal is either of the following two: MSUB_SYNC (either Axial Sync or Table Sync) or Firmware generated signal. Axial Sync is used for all types of axial scans, and Table Sync is used for scout scans. The firmware generated sync signal is used for statics and diagnostic scans.

The exposure command signal goes inactive when either:

The trigger counter expires (by counting either of the synchronization signals mentioned above), or; Enable bit is made inactive, or; The watchdog timer goes out.

2 Watchdog Circuits

The TGP board has two kinds of watchdog timer function:

Internal watchdog: located inside the CPU

External watchdog: located outside the CPU

The internal watchdog deters uncontrolled run of software, if it took place.

The external watchdog must be run to enable the gantry axial drive and x-ray exposure.

3 Control of Gantry Control Panels and Gantry Display

The Gantry user Interface consists of a Gantry display, Gantry push buttons, and the TGP board. Each of these components incorporate a microprocessor. Figure 1 shows the overall design of this control.

Figure 1. Gantry User Interface Design Block Diagram

note:

For a scalable pdf version of this illustration, click on the icon below:

Figure 2. Gantry User Interface Design Block Diagram

211069.pdf

These components are connected by a CAN (Cover-CAN), including the following nodes, in the following quantities:

  • TGP (1)

  • Control panel push buttons (4)

  • Display (1)

The CAN port operates at 250K Baud Rate.

Several functions are common between the three controllers. These functions are:

  • Self Tests

  • Processor Initialization

  • Communication

  • Downloading Code

  • Firmware Revision and Board Revision Reporting

FIRMWARE AND BOARD REVISION

Each microprocessor is able to report its firmware number, firmware revision, board number, board revision, and board serial number. The firmware number and revision number are embedded in the firmware code.

4 Interfaces

4.1 Communication

4.1.1 Ethernet

The Ethernet Controller chip controls the 10Base-T connection with the console.

4.1.2 CAN (Controller Area Network)

The TGP board has two CAN channels: One is Cover-CAN, used for interfacing the gantry push buttons and displays. The other is not used.

The Cover-CAN network supports four (4) control panels: two (2) each on front and rear gantry covers. The Cover-CAN requires the gantry display and one (1) control panel for successful initialization. Upon power-up the TGP tests communications to the gantry display and controllers. Faults are reported as node failures.

4.1.3 LSCOM (Low Speed Communication) via Slip Rings

LSCOM is the communication way between TGP and ORP via slip rings.

It uses three signals: SER_SREF (reference signal), SER_OUTBOUND (transmit signal), and SER_INBOUND (receive signal).

The LSCOM interface needs an isolated +/- 5Vdc bipolar power supply to power the driver/receiver circuits. In addition, optical isolation is maintained between the slip rings and the ORP logic circuits.

4.1.4 EXP_ENBL Signal via Slip Ring

The TGP board outputs EXP_ENBL signal to the ORP board via a slip ring for interrupting EXPCMD signal to JEDI.

4.2 Voltage Monitoring

The TGP provides an A/D interface for monitoring the on-board regulated power supplies: +24V / +12V / +5V.

4.3 Thermal Sensor

The TGP CPU receives signals from thermal sensors: one (LM35DM) is located on the board itself, and the other (LM35DP) is located outside the board.

  • Temperature measurement range: 5 - 65.0 degrees C

  • Accuracy: +/- 1.0 degree C

The signals are converted to digital data by the CPU built-in A/D converter.

4.4 User Interface

4.4.1 Switches

4.4.2 LEDs

4.4.3 Test Pins