Axial Control Theory

The MSUB uses the 82527 CAN protocol controller and CAN bus interface circuitry to communicate with the AMD Assembly. This is a bidirectional serial link. The 82527 interrupts the Altera controller (FPGA) with the AX_DRIVE_COMM* signal to indicate a status change of the 82527. The 82527 communicates with the Altera (FPGA) directly via AXADDR and DATA buses on the MSUB. The 82527 uses the 16MHz clock for timing. The board AXRESET* signal resets the 82527.

U26 and U24 optically isolate the AX_CAN bus from the MSUB board circuitry. U28, the CAN transceiver chip, resides on the isolated side of the CAN interface. The optically isolated side of the AX_CAN receives power from an isolated 12 volt, 125 mA supply located on the AMD. VR1 regulates this 12 volt supply down to 5 volts (+5V_AXCAN). This isolated 5 volt supply provides power to the isolated side of the AX_CAN interface. The AX_CAN output signals are AX_CAN_H and AX_CAN_L. R339 provides the required CAN bus termination for the MSUB Board end of the AX_CAN bus.

DS12 illuminates whenever U26 receives data over the AX_CAN bus.

The communications between the MSUB and AMD consist of:

• Bidirectional CAN serial communications bus: a 125 Kbaud bidirectional serial link, used to convey commands and status information.

• AX_Fault signal from the AMD to MSUB.

• AX_AT-SPD* signal from the AMD to the MSUB.

• AX_AT_FREQ* signal from the AMD to the MSUB.

• AX_AT_POS* signal from the AMD to the MSUB.

• AX_EN_P, AX_EN_N signal from the MSUB to the AMD

• AX_ENC_CHA/CHB signals from the MSUB to the AMD

• Three-wire start-stop signal

The opto-isolated Enable, Start, and Stop signals from the MSUB to the AMD provide a contact closure as an input to the AMD. The Enable contacts close electrically to enable the AMD, the Start contacts close electrically to start the AMD, and the Stop contacts close electrically to enable the AMD to run and open electrically to stop the AMD. The Enable, Start, and Stop opto-isolators carry 10mA with less than a 3V drop when closed, and withstand 5V when the contacts open.

The fault signal from the AMD to the MSUB consists of the AX_FLT and AX_FLT_RTN signal wires. The circuit uses drives with a normally-open fault contact. If either the fault signal wires open electrically, the MSUB generates a fault condition. If the AX_SPD_FRQ_RTN signal wire opens during operation, the system can report either AX_AT_SPD or AX_AT_FREQ errors.

The AX_AT_SPD*, AX_AT_FREQ* AND AX_AT_POS* are active low or NO FAULT conditions during normal axial operations. These signals should be high with the gantry rotation idle. The AX_FLT is a normally low signal. If this signal goes high, then the AX_FAULT_CONTACTS in the AMD have opened and you have a fault.

If the motor is at or above Frequency for the phase it is currently in, then AT SPEED will be satisfied and closes. AT SPEED will then open when the phase changes transition, and waits for the motor to be at or above Frequency again for this next phase, then will close if the motor reaches Frequency. This will continue throughout the entire rotation cycle, Accel, Run, and Brake. It is key to know that the AMD module will try to drive the motor to the correct speed, and if it cannot attain the speed requested, the current will max out at a specific level and not drive any higher, the result will be that the motor could not make it to the correct frequency in the allotted time for that phase, and the AT SPEED fault will be seen.

The discrete start and stop signals to the AMD are opto-coupled logic signals. The STOP_AXIAL signal must equal a logic high for the AMD to start acceleration, continue acceleration or run. The logic high STOP_AXIAL signal creates a low impedance between the STOP_AXIAL and STRT_STP_COM output signals, which permits the AMD to accelerate or run.

When the START_AXIAL signal goes to a logic high (causing a low impedance between the START_AXIAL and STRT_STP_COM outputs) and the STOP_AXIAL signal equals a logic high, the AMD begins to accelerate (if it hasn’t already done so). Once acceleration begins, the AMD continues to advance along its acceleration profile, or continues to run, regardless of the logic condition of the START_AXIAL signal. The AMD begins to decelerate (if it is running) whenever the STOP_AXIAL signal goes to a logic low.

This function is performed within the AMD module. Errors are reported to the MSUB Board.

CAN implements five error detection mechanisms: three at the message level and two at the bit level.

The following mechanisms are at the message level:

• Cyclic Redundancy Checks (CRC) - Every transmitted message contains a 15 bit Cyclic Redundancy Check (CRC) code. The CRC is computed by the transmitter and is based on the message content. All receivers that accept the message perform a similar calculation and flag any errors.

• Frame Checks - There are certain predefined bit values that must be transmitted at certain points within any CAN Message Frame. If a receiver detects an invalid bit in one of these positions, a Form Error (sometimes also known as For at Error) will be flagged.

• Acknowledgement Error Checks - If a transmitter determines that a message has not been acknowledged, then an ACK Error is flagged.

The following mechanisms are at the bit level:

• Bit Monitoring - Any transmitter automatically monitors and compares the actual bit level on the bus with the level that it transmitted. If the two are not the same, then a bit error is flagged.

• Bit Stuffing - CAN uses a technique known as bit stuffing as a check on communication integrity. After five consecutive identical bit levels have been transmitted, the transmitter will automatically inject (stuff) a bit of the opposite polarity into the bit stream. Receivers of the message will automatically delete (de-stuff) such bits before processing the message in any way. Because of the bit stuffing rule, if any receiving node detects six consecutive bits of the same level, a stuff error is flagged.

The Axial Motor Drive is a customized version of a commercially available Allen-Bradley Model 1336 Plus II variable frequency AC motor drive. It contains its own microprocessor, power supplies and a three-phase full bridge inverter. The AMD communicates with the MSUB board through a CAN (Controller Area Network) serial bus.

The AMD Control board jumpers are all factory default settings. See Figure 3 for specifics.

Figure 3. Axial Motor Drive Control Board Jumpers

The AMD Encoder board jumpers J1 and J2 should be set for 5V.

Figure 4. Axial Motor Drive Encoder Board Jumpers

The Dynamic Brake board Chopper circuit helps dissipate excess energy in the Axial Motor Drive’s internal AXDC bus. The Chopper circuit is always active in this application. As the motor decelerates, it acts as a generator, which converts some of the kinetic energy to current. The Axial Motor Drive channels this current into the AXDC bus, which causes the voltage on the bus to rise. If the bus voltage exceeds 810V, the drive will disable itself and abort the braking process. When the braking process aborts, the gantry coasts to a stop. The chopper circuit limits the bus voltage to approximately 750V to prevent the gantry from coasting.

The Axial Motor Drive’s AXDC voltage powers the circuit at J1 of the Dynamic Brake board. Two 7500 ohm 40W chassis mounted dropping resistors, connected at J1 and J2, limit the power supply current to <50 mA. CR4 regulates the nominal 15V to power the Chopper Control circuit. LED DS1 illuminates to indicate the presence of circuit power.

The filter board adds differential mode and common mode capacitance to the Axial Motor Drive internal AXDC bus, to reduce the electrical noise created by the switching IGBTs. This board is required for EMI/EMC compatibility.

The chopper resistor assembly provides a high power dissipation load to the AMD bus, if required during axial braking. The chopper resistor configuration resembles the shunt regulator. The Dynamic Brake board contains the actual chopper switching element (an IGBT).

When the axial induction motor brakes, it can momentarily generate a current. When this happens, the AMD converts some of the rotational energy to electrical energy and returns it to the internal AXDC bus causing a rise in the bus voltage. If the AXDC bus voltage exceeds ~750V, the chopper IGBT turns on and discharges the excess energy through resistors A4R1, A4R2, A4R3, and A4R4. The IGBT turns off when the voltage drops below ~700V. This process continues as long as necessary to keep the bus voltage below ~750V. Normally this action occurs for less than 5 seconds during the brake cycle. At all other times the IGBT remains off and essentially “disconnects” the resistors from the bus. The intermittent duty cycles permits the use of resistors with a much lower power rating than a continuous duty cycle would require.

Because the circuit uses the intermittent duty rated resistors A4R1, A4R2, A4R3, and A4R4, it contains fuse A4F1 to isolate the resistors from the bus in the event of a control failure. If a fault occurs, A4SCR1 fires and crowbars the bus. The anode of A4SCR1 connects to taps on resistor A4R1 and A4R2, nominally set to 8 ohms each from the fused end. When the SCR fires, the high current load it creates causes fuse A4F1 to open and disconnect the resistor assembly from the bus, to isolate the fault.

500VA isolation transformer, T1, is configured as a nominal 115:380 V step-up transformer. T1 provides the 24 hour power to the AMD that is needed to maintain communication with the MSUB. Diodes inside the AMD rectify the ~380VAC to create a nominal 500 VDC bus (no load, with 120 VAC input). DC to DC converters inside the drive develop power for its internal logic from this bus. T1 should normally never provide power for axial braking.

Bridge Rectifier CR1 connects in series between the T1 step-up transformer and the AMD AXDC bus as the logic and control power source for the drive. The drive internal bus voltage always equals the greater of either the braking voltage or the T1 voltage.

Chassis mounted dropping resistors R4 and R5 limit the chopper circuit power supply current derived from the AMD AXDC bus to <50 mA. The Chopper Control supply is referenced to the AXDC bus return, NOT to ground. NEVER reference this voltage to ground.