Collimator Theory of Operation

Table 1 lists the major functions of the CCB.

Figure 1 shows the location of parts on the CCB.

Figure 1. Location of Parts (CCB)

This comes with a 16 MHz clock and the Standard TPU (Time Processor Unit) with enhanced PPWA (Period/Pulse-Width Accumulator). The TPU is essentially a dedicated processor for time related functions.

The processor clock is derived off a 32.000MHz crystal oscillator, which is divided down to 16 Hz, which is fed into the processor. The clock runs through the processor and exits the chip at the CLKOUT pin before feeding the rest of the board. If the clock stops for over 9.9 mS, the missing pulse detector will pull the reset bus line low and set the clock loss bit in the Altera. This bit can only be reset by firmware command (or power cycling).

There is one central Reset line on the CCB. This central line connects the CPU, the pushbutton reset, the external GCAN reset, the Background Debugging Mode connection, the Altera, and the 82527 CAN controller.

The external GCAN reset is applied by commanding GCAN_RST_P high relative to GCAN_RST_N. This puts the board into reset.

The CPU does not interface directly to any external devices. It buffers the signals through HCT244 devices. The following are inputs from external devices:

The CAM and Filter encoder signals are buffered inputs to the TPU as are the filter home switch and the DAS trigger signal. The Filter C pulse and the filter home switch are combined to form the filter home signal. The TPU is set up to decode the quadrature of the encoders and provides a 16 bit counter for each axis position.

The filter home switch contacts and the filter encoder C pulse are also buffered to the DATA bus through the “INREG” register (U24). That is the only register outside of the Altera used for data.

Outputs from the TPU are for the CAM and filter drives and these are buffered out through an HCT244.

The TPU has a stepper motor control algorithm that is used for the CAM drives. The firmware sets of the TPU with the acceleration and deceleration rates and the step rate. When it sets the desired position the TPU takes care of the actual move. It is set up now for half step commands to the Vexta 5 phase stepper driver at a rate of 2000 steps per second for a standard aperture move.

The RS232 link is on the board purely for development reasons.

The Data3, Data9 are held low on reset to configure the 68332. Data3 low on reset release configures the /CS6 pin to be ADDR19 so we can access 1 MB of memory. Data9 low on release of reset turns the IRQ[7:1] lines into PortF outputs. Holding MODCLK low configures the 68332 to use an external clock source.

The memory for the CCB consists of 8 Mbit (1 Mbyte) of 120 nS FLASH and the same amount of 55 nS RAM. The FLASH interfaces directly to the 68332. The RAM does not. The DCB uses the the same boot firmware. ADDR0 is not used on the memory. The read/write decode from the Altera handles the byte selection.

The CAN controller chip is an Intel 82527. Firmware writes and reads from this chip to send and receive messages via the CAN. When pin 2 of the HCPL7101 is high, the output (pin 6) is high. The outputs (pins 6 and 7) of the 82C250 will be floating. This is the “recessive” bus state on the network. A logic zero from the 82527 will result in GCH (Gantry Can High) being pulled to high and GCL (Gantry Can Low) being pulled low.

The 82527 has two ports on it: one is used as the data bus interface to the rest of the board; the other is used to light LEDs. The function of these LEDs are defined by firmware.

The CAM drive function consists of the clockwise and counterclockwise pulse commands to the stepper motor driver, encoder feedback, the driver disable signal and the driver current cutback inhibit signal. The clockwise and counter-clockwise pulses are derived in the Altera from quadrature pulses created by the TPU in the 68332. The rate of these is under firmware control. The TPU also decodes the encoder signals to keep track of the count and direction of movement.

Two control signals from the 68332 are for controlling the behavior of the Vexta, 5 phase stepping motor driver. Essentially the 68332 writes to a register to set the signals CURR_HOLD and CAM_OFF_OUT.

When CURR_HOLD is high, it turns on FET Q35 and prevents the stepping motor driver from automatically decreasing its drive to the motor. Normally the current gets cut back by half after a move because it is not needed for acceleration and movement.

When the CAM_OFF_OUT signal goes high, it turns on a FET Q36, which turns off the stepping motor driver and allows the CAMS to “freewheel”.

The filter driver is a basic H-bridge with high side current sensing for each phase. Sensing the high side allows protection for output shorts to ground. The stepping signals come from the TPU and decoded by the Altera to sequence the high and low FET drive signals.

The current limit circuitry is the same for both phases. An instrumentation amplifier with high common mode rejection senses the current through an effective 0.25 ohm resistance. The output of the amplifier is then fed into two comparators. One comparator is for pulse to pulse current limiting and the other is the short circuit latch comparator. For pulse to pulse current limit, the voltage regulators are divided down to create a reference voltage. This reference is fed into the comparator and when the output from the sensed current exceeds the reference, the comparator switches and shuts off a latch, which turns off the top FET. This cycles at a 15 kHz rate because of the clock into the latch.

The short circuit protection circuitry uses the same concept as the pulse to pulse limit except on a short, the rate of rise of the current is so fast that the current sensed can rise to just over 10 A. This is limited by the 6.8 uH inductor on the board and the reverse recovery charge of the lower FET's parasitic diode. As the current passes the short circuit reference voltage, a comparator switches in a latch that cuts off drive to the top FETs. Only firmware can reset this latch so current stays off after a short until firmware commands otherwise.

The Current Cut back function drops the current to the filter. This keeps the motor from unnecessarily dissipating power when it is not moving. The firmware can command this, which then turns on Q5. When Q5 is on, it drops the pulse to pulse current reference.

The H-bridge uses two high side gate driver chips per phase. These create floating voltages to drive the top FETs without transformers or optical circuitry. The resistor - diode combinations around the inverters which feed the gate driver chips and the gates of the FETs are set up to prevent "shoot through" or simultaneous conduction. This is prevented by turning on the FETs slow and turning them off fast. The SD signal into the ir2110 devices disables drive until a command occurs. Holding SD high disables the driver.

The filter home switch tells the CCB when the filter is physically positioned “at home” of course. It does this by feeding back the normally open and normally closed contact signals, which can be read at register U24 (Address 0x800000/1 in the memory map). When at home, the normally open switch is closed and the normally closed switch is closed.

The voltage regulators create voltages for the FET gate drivers (12V), and the instrumentation amp (± 8V). The 8V signal is for the pulse to pulse and short circuit currents.

The Altera functionality is covered in the Programmable Device Logic (PDL) specification 2208487PDL.

With the exception of the INREG register (Address 0x800000), the input and output registers are in the Altera.

• The purpose of tracking is to follow the focal spot so that the system can keep the umbra of the beam on the detector to reduce dose and still avoid artifacts.

• Dose reduction is approx. 40% less in the 4 x 1.25mm mode and 25% less in the 4 x 5.00 mode.

• Z-Axis tracking is needed because the focal spot moves in Z due to thermal changes in the tube, and in mechanical forces during Gantry rotation and tilt.

• Z-Axis tracking involves the X-Ray Tube Focal Spot, Collimator, Detector, DAS, DCB, CCB, and RCIB/GCAN Communication Networks.

Figure 2. Typical Tracking Feedback Loop

The purpose of tracking is to follow the focal spot so that we can keep the uniform X-ray of the narrowest possible beam on the detector to reduce dose and still avoid artifacts. The focal spot moves in Z due to thermal changes in the tube and a mechanical forces during gantry rotation and tilt angle. Each cam is basically an independent system.

Figure 3. Tracking Diagram

1. Select a safe operating point at the edges of the detector (target beam position at isocenter).

2. Sample X-ray beam position every view and adjust collimator CAM positions every 20 ms. to keep the beam at the ISO center channel operating point.

   1. Compute Z ratio for each side of the Z module (outer row)/ (inner row). (Channels 763, 764, 765, 766, 767 & 768.)

   2. Convert the ratio to a beam position at the Z module.

   3. Compute the focal spot position given the beam position on the Z module, the cam position for the Z module, and geometric magnification factors at the Z module.

   4. Compute the new cam position for the isocenter channel given the focal spot position and geometric magnification factors for the isocenter channel. During views when portions of the patient, patient table, IV line etc. block the Z module, the beam position measurement can not be used.

   5. We will compare DAS data channel 762 (data channel adjacent to the Z module) to an expected signal as a function of the measured mA, DAS gain, and trigger period. The Z module is blocked if either inner row is less than 0.9 times the expected value. During a blocked condition, the cams will hold constant at the last unblocked position.

      note: Transient conditions during a tube spit do not require special action.

   6. Measure the beam position and readjust the collimator approximately every 20 ms.

3. Scan aborts will occur when the following conditions exist.

   1. Beam position on detector, non-blocked z-chnls condition, is out of tolerance by +/- 0.4 mm of desired position for more than 100 mSec.

   2. Signal Corruption of chnls 762 through 768, where zero or negative values (counts) are detected for more than 200 mSec OR generator mA feedback to DCB is less than 4 mA for more than 200 mSec.

   3. Focal spot length error for more than 4000 mSec

Figure 4. Z Sensing Module

• Collimator Functional Diagnostic Tests.

• Diagnostic Data Collection Tool.

  • FET Override mode

  • Create and apply non-tracking Cal and DDC Scan

Z-AXIS ERROR CODES

Many of these messages contain variable fields for which some text or values will be substituted.